`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/10/23 15:21:30
// Design Name: 
// Module Name: maindec
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module maindec(
	input wire[5:0] op,
    input wire[5:0] funct, 
	output wire memtoreg,memwrite,
	output wire branch,alusrc,
	output wire regdst,regwrite,
	output wire jump,
	output wire signextend,
	output wire[7:0] alucontrol
    );
	reg[15:0] controls;
	assign {regwrite,regdst,alusrc,branch,memwrite,memtoreg,jump,signextend,alucontrol} = controls;
	always @(*) begin
		case (op)
//			6'b000000:controls <= 9'b110000010;//R-TYRE
//			6'b100011:controls <= 9'b101001000;//LW
//			6'b101011:controls <= 9'b001010000;//SW
//			6'b000100:controls <= 9'b000100001;//BEQ
//			6'b001000:controls <= 9'b101000000;//ADDI
//			6'b000010:controls <= 9'b000000100;//J
//			default:  controls <= 9'b000000000;//illegal op
            6'b001100:controls <= 16'b1010000100010001;  //addi
            6'b001110:controls <= 16'b1010000100010011;  //xori
            6'b001111:controls <= 16'b1010000100010101;  //lui
            6'b001101:controls <= 16'b1010000100010010;  //ori
            default: case(funct)
                6'b100100: controls <= 16'b1100000000010001;  //add
                6'b100101: controls <= 16'b1100000000010010;  //or
                6'b100110: controls <= 16'b1100000000010011;  //xor
                6'b100111: controls <= 16'b1100000000010100;  //nor
                6'b000000: controls <= 16'b1100000000100001;  //sll
                6'b000010: controls <= 16'b1100000000100010;  //srl
                6'b000011: controls <= 16'b1100000000100011;  //sra
                6'b000100: controls <= 16'b1100000000100100;  //sllv
                6'b000110: controls <= 16'b1100000000100110;  //srlv
                6'b000111: controls <= 16'b1100000000100111;  //srav
                default: controls <= 16'b0;
            endcase
		endcase
	end
endmodule